Time and Venue: Tuesday, July 17, 13:30 p.m. – 15:35 p.m, Ada Lovelace Room, Lab’O, Orléans Val de Loire Technopole Orléans, France
Chairs: Syed Waqar Nabi, H.M.S. Weearathne
(University of Glasgow, U.K.; University of Moratuwa, Moratuwa, Sri Lanka)
Herman Lam, NSF SHREC Center, University of Florida – Gainesville, Florida, USA (http://www.hlam.ece.ufl.edu/)
Herman Lam is an Associate Professor of Electrical and Computer Engineering at the University of Florida. He also serves as the Associate Director of CHREC, the NSF Center for High-Performance Reconfigurable Computing. He has over 25 years of research and development experience in the areas of distributed computing, service-oriented computing, and database management. Currently, Dr. Lam’s main research interests in reconfigurable computing (RC) focus upon methods and tools for the acceleration and deployment of scientifically impactful applications on scalable RC systems like the Novo-G reconfigurable supercomputer. He has authored or co-authored over 100 refereed conference and journal articles and one textbook. Since 2007, he has obtained research funding in the amount of $464,000 as PI and $2,806,000 as Co-PI. He is a Co-PI of the 2012 Alexander Schwarzkopf Prize for Technology Innovation from the National Science Foundation for “Novo-G: An innovative and synergistic research project and the world’s most powerful reconfigurable supercomputer”.
In addition, Dr. Lam is the Director of the Computer Engineering undergraduate program in the College of Engineering at the University of Florida. He has earned numerous teaching awards, including awards for co-chairman of a best Ph.D. dissertation in his department, outstanding supervisor of a core laboratory in his department, and outstanding teaching award in the College of Engineering, and UF University Teaching Improvement Program (TIP) award.
Éric Rutten, T Universite Grenoble Alpes, Inria, CNRS, Grenoble INP, LIG, Grenoble, France (https://team.inria.fr/ctrl-a/members/eric-rutten/)
Éric Rutten is an INRIA researcher at INRIA Grenoble Rhône-Alpes. He leads the Inria team Ctrl-A. His main research interest is in the model-based control of autonomic, adaptive and reconfigurable computing systems, also called feedback computing.
13:30-14:00: Invited Talk: Autonomic Management of Reconfigurations in DPR FPGA-based Embedded System
Soguy Mak-Karé Gueye, Éric Rutten, Jean-Philippe Diguet
14:00-14:30: Invited Talk: Research Opportunities in Heterogeneous Computing for Machine Learning
Herman Lam, David Ojika
14:30-14:50: OpenCL Performance Prediction using Architecture-Independent Features
Beau Johnston, Gregory Falzon, Josh Milthorpe
14:50-15:10: Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J, Linga Reddy Cenkeramaddi
15:10-15:30: Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs
Syed Waqar Nabi, Wim Vanderbauwhede
Camera Ready papers to be submitted on the parent conference website. See instructions here: http://hpcs2018.cisedu.info/6-participants/author-s-info-hpcs2018
The International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN-2018) is part of the The International Conference on High Performance Computing & Simulation (HPCS 2018). Please visit the conference website for more information on: venue and local details, registration, travel and visa.
- Topics of interest
- Important dates
- Information about proceedings
- Call for Papers
- Instructions for participants
- Organizers and program committee
Reconfigurable Systems (RS) and Networks on Chips (NoC) are increasingly finding use in applications that require high-performance computing (HPC), power-efficiency, or both. Field-Programmable Gate Arrays (FPGAs) are seeing adoption in mainstream for both big-data and big-compute applications. The use of NoCs – as opposed to conventional bus-based communication architectures – is already established in a variety of architectures.
While there is considerable maturity in the area of NoC and RS architectures, there is a gap between the capability of such architectures, and the capability of programmers, compilers, and runtime systems to efficiently exploit the performance and efficiency dividends these architectures promise.
More specifically, the challenges — and the corresponding opportunity for innovation — can be broken down into four broad categories: programming, compilers, run-time infrastructures, and the architectures themselves. Wider adoption, especially of reconfigurable systems, is contingent on a synergetic development and maturity across these areas. Lack of such a synergy has been a major hurdle to RS and specifically FPGAs becoming more mainstream, but there are very strong indicators in the academia and the industry that this is changing. High Performance Reconfigurable Computing (HPRC) is specially getting widespread interest.
The International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN 2018) is intended to serve as a forum and bring together researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of reconfigurable systems and NoCs in high-performance and/or power-efficient systems. The challenges to wider adoption of these technologies, arising out of programming environments, compilers, and run-time systems are of special interest to this workshop, along with innovations at the architectural level.