[*FINAL*  paper submission deadline 14th April].

Reconfigurable Systems (RS) and Networks on Chips (NoC) are increasingly finding use in applications that require high-performance computing (HPC), power-efficiency, or both. Field-Programmable Gate Arrays (FPGAs) are seeing adoption in mainstream for both big-data and big-compute applications. The use of NoCs – as opposed to conventional bus-based communication architectures – is already established in a variety of architectures.

While there is considerable maturity in the area of NoC and RS architectures, there is that familiar gap between the capability of such architectures, and the capability of programmers, compilers, and runtime systems to efficiently exploit the performance and efficiency dividends these architectures promise.

More specifically, the challenges — and the corresponding opportunity for innovation — can be broken down into four broad categories: programming, compilers, run-time infrastructures, and the architectures themselves. Wider adoption, especially of reconfigurable systems, is contingent on a synergetic development and maturity across these areas. Lack of such a synergy has been a major hurdle to RS and specifically FPGAs becoming more mainstream, but there are very strong indicators in the academia and the industry that this is changing. High Performance Reconfigurable Computing (HPRC) is specially getting widespread interest.

The International Workshop on High Performance Dynamic Reconfigurable Systems and Networks (DRSN 2016) is intended to serve as a forum and bring together researchers and engineers in both academia and industry to exchange ideas, share experiences, and report original works about all aspects of reconfigurable systems and NoCs in high-performance and/or power-efficient systems. The challenges to wider adoption of these technologies, arising out of programming environments, compilers, and run-time systems are of special interest to this workshop, along with innovations at the architectural level.

This workshop is part of the The International Conference on High Performance Computing & Simulation (HPCS 2016). Please visit the conference website for more information on:  venue and local details, registration, travel and visa.

Use these links or from the top of the page for information specific to this workshop, that is:

And click here for stunning views from a panoramic webcam in the venue city, Innsbruck, Austria.